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HM514260C Series HM51S4260C Series
262,144-word x 16-bit Dynamic Random Access Memory
ADE-203-260A (Z) Rev. 1.0 Jun. 12, 1995
Description
The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word x 16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation.
Features
* * * Single 5 V (10%) (HM51(S)4260C-6/7/8) (5%) (HM51(S)4260C-6R) High speed -- Access time: 60 ns/70 ns/80 ns (max) Low power dissipation -- Active mode: 825 mW/788 mW/770 mW/688 mW (max) -- Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8) 10.5 mW (max) (HM51(S)4260C-6R) 1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4260C-6R) Fast page mode capability 512 refresh cycles: 8 ms 128 ms (L-version) 2 CAS-byte control 2 variations of refresh -- RAS-only refresh -- CAS-before-RAS refresh Battery backup operation (L-version) Self refresh operation (HM51S4260C)
* * * *
* *
HM514260C, HM51S4260C Series
Ordering Information
Type No. HM514260CJ-6 HM514260CJ-6R HM514260CJ-7 HM514260CJ-8 HM514260CLJ-6 HM514260CLJ-6R HM514260CLJ-7 HM514260CLJ-8 HM51S4260CJ-6 HM51S4260CJ-6R HM51S4260CJ-7 HM51S4260CJ-8 HM51S4260CLJ-6 HM51S4260CLJ-6R HM51S4260CLJ-7 HM51S4260CLJ-8 HM514260CTT-6 HM514260CTT-6R HM514260CTT-7 HM514260CTT-8 HM514260CLTT-6 HM514260CLTT-6R HM514260CLTT-7 HM514260CLTT-8 HM51S4260CTT-6 HM51S4260CTT-6R HM51S4260CTT-7 HM51S4260CTT-8 HM51S4260CLTT-6 HM51S4260CLTT-6R HM51S4260CLTT-7 HM51S4260CLTT-8 Access Time 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 400-mill 44-pin plastic TSOP II (TTP-44/40DB) Package 400-mill 40-pin plastic SOJ (CP-40DA)
2
HM514260C, HM51S4260C Series
Pin Arrangement
HM514260CJ/CLJ Series HM51S4260CJ/CLJ Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
HM514260CTT/CLTT Series HM51S4260CTT/CLTT Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8
(Top view)
NC NC WE RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
(Top view)
Pin Description
Pin Name A0 to A8 Function Address input -Row address -Column address -Refresh address Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground No connection A0 to A8 A0 to A8 A0 to A8
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
3
I/O5
I/O7 I/O6 I/O4
WE
I/O5 Buffer I/O4 Buffer I/O6 Buffer I/O7 Buffer
RAS
Row Decoder
Block Diagram
Row Decoder
256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder
Row Decoder I/O3 I/O3 Buffer
Selector
Selector
I/O Bus & Column Decoder
Address
I/O2
I/O2 Buffer
256 k Memory Array Mat
Row Row Decoder Decoder
Row Row Decoder Decoder
256 k Memory Array Mat
I/O1 I/O1 Buffer
Selector
Selector
I/O Bus & Column Decoder
Row Decoder
HM514260C, HM51S4260C Series
A0,A1,A2,A3
256 k Memory Array Mat
I/O0 I/O0 Buffer
256 k Memory Array Mat
Peripheral Circuit
4
I/O15 I/O15 Buffer Row Decoder I/O14 I/O14 Buffer
Peripheral Circuit
Peripheral Circuit
Row Decoder
256 k Memory Array Mat
256 k Memory Array Mat
Address A4,A5
Selector
Selector
I/O Bus & Column Decoder
I/O Bus & Column Decoder 256 k Memory Array Mat
I/O13 I/O13 Buffer
256 k Memory Array Mat
Row Row Decoder Decoder
Row Row Decoder Decoder
A6,A7,A8
256 k Memory Array Mat
256 k Memory Array Mat
Selector
Selector
I/O Bus & Column Decoder
Row Decoder
I/O Bus & Column Decoder
I/O12 I/O12 Buffer Row Decoder
256 k Memory Array Mat
256 k Memory Array Mat
I/O11 Buffer I/O9 Buffer I/O8 Buffer
I/O10 I/O10 Buffer
I/O11
I/O8
I/O9
LCAS
UCAS OE
HM514260C, HM51S4260C Series
Operation Mode
The HM51(S)4260C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read- modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle(HM51S4260C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read- modify-write cycle
Inputs RAS H H L L L L L H to L LCAS H L L L L L H H L L L L L L L H to L H to L H to L H to L L UCAS H L L L L L H L H L H to L H to L H to L H to L L H L* L*
2 2
WE D H H L* L*
2 2
OE D L L D H L to H D D
Output Open Valid Valid Open Undefined Valid Open Open
Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4260C)
H to L D D
L D H L to H H
Valid Open Undefined Valid Open
Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read-modify-write cycle Read cycle (Output disabled)
H to L H
Notes: 1. H: High(inactive) L: Low(active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
5
HM514260C, HM51S4260C Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)*2
Parameter Supply voltage Symbol VSS Min 0 Typ 0 5.0 5.0 -- -- Max 0 5.5 5.25 6.5 0.8 Unit V V V V V Notes 2 1, 2 1, 2 1 1
VCC (HM51(S)4260C-6/7/8) 4.5 VCC (HM51(S)4260C-6R) Input high voltage Input low voltage VIH VIL 4.75 2.4 -1.0
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
6
HM514260C, HM51S4260C Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4260C-6R) (Ta = 0 to 70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4260C-6/7/8)
HM514260C, HM51S4260C -6/-6R Parameter Operating current*1, *2 Standby current -7 -8 RAS, UCAS or LCAS cycling t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS, WE, OE V CC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS, OE, WE V CC - 0.2 V Dout = High-Z t RC = min RAS = VIH, UCAS or LCAS = VIL Dout = enable t RC = min t PC = min Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 s t RAS 1 s, UCAS, LCAS = VIL WE, OE = VIH CMOS interface RAS, UCAS, LCAS 0.2 V, Dout = High-Z CMOS interface RAS, UCAS, LCAS 0.2 V, Dout = High-Z
Symbol Min Max Min Max Min Max Unit Test Conditions I CC1 I CC2 -- -- 150 -- 2 -- 140 -- 2 -- 125 mA 2 mA
--
1
--
1
--
1
mA
Standby current (L-version)
I CC2
--
200 --
200 --
200 A
RAS-only refresh current*2 Standby current *1 CAS-before-RAS refresh current *2 Fast page mode current*1, *3 Battery backup current*4 (Standby with CBR refresh) (L-version) Self-refresh mode current (HM51S4260C) Self-refresh mode current (HM51S4260CL)
I CC3 I CC5 I CC6 I CC7 I CC10
-- -- -- -- --
140 -- 5 --
130 -- 5 --
110 mA 5 mA
140 -- 150 -- 300 --
130 -- 130 -- 300 --
110 mA 120 mA 300 A
I CC11
--
1
--
1
--
1
mA
I CC11
--
200 --
200 --
200 A
7
HM514260C, HM51S4260C Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4260C-6R) (Ta = 0 to 70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4260C-6/7/8) (cont)
HM514260C, HM51S4260C -6/-6R Parameter Input leakage current Output leakage current -7 -8 A A V V 0 V Vin 6.5 V 0 V Vout 6.5 V, Dout = disable High Iout = -5.0 mA Low Iout = 4.2 mA
Symbol Min Max Min Max Min Max Unit Test Conditions I LI I LO -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4
Output high voltage VOH Output low voltage VOL
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH V CC - 0.2 V, 0 V IL 0.2 V, Address can be changed once or less while RAS = VIL 5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage.
Capacitance (Ta = +25C, VCC = 5 V 5%) (HM51(S)4260C-6R) (Ta = +25C, VCC = 5 V 10%) (HM51(S)4260C-6/7/8)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout
8
HM514260C, HM51S4260C Series
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4260C-6R)*1, *14, *15, *17, *18 (Ta = 0 to 70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4260C-6/7/8)*1, *14, *15, *17, *18
Test Conditions * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (50 pF) (HM51(S)4260C-6R) (Including scope and jig) 2 TTL gate + CL (100 pF) (HM51(S)4260-6/7/8) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
HM514260C, HM51S4260C -6/-6R Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min Max t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF t REF 110 -- 40 60 15 0 10 0 15 20 15 15 60 10 15 0 0 3 -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 8 128 -7 Min Max 130 -- 50 70 20 0 10 0 15 20 15 20 70 15 20 0 0 3 -- -- -- 10000 10000 -- -- -- -- 50 35 -- -- -- -- -- -- 50 8 128 -8 Min Max 150 -- 60 80 20 0 10 0 15 20 15 20 80 15 20 0 0 3 -- -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- -- -- -- 50 8 128 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 20 19 19 8 9 23
9
HM514260C, HM51S4260C Series
Read Cycle
HM514260C, HM51S4260C -6/-6R Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min Max t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD -- -- -- -- 0 0 0 30 0 0 15 60 15 30 15 -- -- -- -- 15 15 -- -7 Min Max -- -- -- -- 0 0 0 35 0 0 15 70 20 35 20 -- -- -- -- 15 15 -- -8 Min Max -- -- -- -- 0 0 0 40 0 0 15 80 20 40 20 -- -- -- -- 15 15 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns 6 6 2, 3 3, 4, 13 3, 5, 13 23 19 16, 19 16
Write Cycle
HM514260C, HM51S4260C -6/-6R Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time CAS to OE delay time Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH t COD 0 15 10 20 20 0 15 -- -- -- -- -- -- -- -- 0 -7 Min Max 0 15 10 20 20 0 15 -- -- -- -- -- -- -- -- 0 -8 Min Max 0 15 10 20 20 0 15 -- -- -- -- -- -- -- -- 0 Unit Notes ns ns ns ns ns ns ns ns 21 11 11 23 10, 19 19
10
HM514260C, HM51S4260C Series
Read-Modify-Write Cycle
HM514260C, HM51S4260C -6/-6R Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min Max t RWC t RWD t CWD t AWD t OEH 150 -- 80 35 50 15 -- -- -- -- -7 Min Max 180 -- 95 45 60 20 -- -- -- -- -8 Min Max 200 -- 105 -- 45 65 20 -- -- -- Unit Notes ns ns ns ns ns 10 10 10, 13
Refresh Cycle
HM514260C, HM51S4260C -6/-6R Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol Min Max t CSR t CHR t RPC t CPN 10 10 10 10 -- -- -- -- -7 Min Max 10 10 10 10 -- -- -- -- -8 Min Max 10 10 10 10 -- -- -- -- Unit Note ns ns ns ns 19 20 19 22
Fast Page Mode Cycle
HM514260C, HM51S4260C -6/-6R Parameter Fast page mode cycle time Fast page mode CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol Min Max t PC t CP t RASC t ACP t RHCP 40 10 -- -- 35 55 80 -- -- -7 Min Max 45 10 -- -- -8 Min Max 50 10 -- -- Unit Notes ns ns 22 12 3, 13, 20
100000 -- 35 -- -- -- -- 40 65 95
100000 -- 40 -- -- -- -- 45 70
100000 ns 45 -- -- ns ns ns ns
Fast page mode read-modify-write cycle t CPW CAS precharge to WE delay time Fast page mode read-modify-write cycle t PCM time
100 --
11
HM514260C, HM51S4260C Series
Self refresh Mode
HM51S4260C -6/-6R Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min Max t RASS t RPS t CHS 100 -- 110 -- -50 -- -7 Min Max 100 -- 130 -- -50 -- -8 Min Max 100 -- 150 -- -50 -- Unit Notes s ns ns 21 24, 25, 26
Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF (HM51(S)4260C-6/7/8), 2 TTL 50 pF (HM51(S)4260C-6R). 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD t CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UCAS and LCAS go low at the same time, all 16-bits data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 20. t CRP , t CHR, t ACP, tRCH and t CPW are determined by the later rising edge of UCAS or LCAS. 21. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS.
12
HM514260C, HM51S4260C Series
22. t CPN and t CP are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 24. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) Invalid Dout
A @ A @
13
HM514260C, HM51S4260C Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. UCAS/LCAS are allowed under the following conditions. However skew between
(1) Each of the UCAS/LCAS should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
Early write
LCAS
WE
(3) Closely separated upper/lower byte control is not allowed. However when the condition (tCP tU L) is satisfied, fast page mode can be performed.
RAS
UCAS
LCAS
t UL
14
HM514260C, HM51S4260C Series
Timing Waveforms*27
Read Cycle
t RC t RAS
RAS tT t RCD t RSH t CAS t CSH t RP t CRP
UCAS LCAS t ASR t RAD t RAH t ASC t RAL t CAH
Address
Row
Column
t RCS
t RCH
WE t CAC t AA High-Z Dout t RAC t DZC Din High-Z t OAC
t RRH t OFF1
Dout t OFF2 t CDD
t ODD t DZO
OE
15
HM514260C, HM51S4260C Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
t RP
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z
* OE : H or L
16
HM514260C, HM51S4260C Series
Delayed Write Cycle
t RC t RAS t RP
RAS t CSH tT t RCD UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RWL t RSH t CAS t CRP
Address
Row
t RCS
t WP
WE t DH t DS
t DZC t DZO t ODD t OEH Dout High-Z t COD *Invalid Dout t OFF2 OE * Do not enable Dout during delayed write cycle. 17
Din
Din
HM514260C, HM51S4260C Series
Read-Modify-Write Cycle
t RWC tT t RP
RAS t CRP t RCD UCAS LCAS t ASR t RAH t RAD t ASC t CAH
Address
Row t RCS
Column t CWL t CWD t AWD t WP t RWL
WE t RWD
t AA
t CAC t RAC t DZC Din High-Z t DS
t DH
Din
Dout
High-Z t OAC
Dout t OFF2 t DZO t ODD
t OEH
OE
18
HM514260C, HM51S4260C Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP UCAS LCAS t RAH t ASR Address Row t RPC t CRP
Dout
High-Z
* OE, WE : H or L ** Refresh address : A0 - A8 (AX0 - AX8)
19
HM514260C, HM51S4260C Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS ** t RP t RC t RAS **
t RP
RAS tT t RPC t CPN UCAS LCAS t RPC t CSR t CHR t CPN t CSR t CHR t CRP
Address t OFF1 Dout High-Z 20
* WE : H or L
> ** Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514260C).
HM514260C, HM51S4260C Series
Fast Page Mode Read Cycle
t RASC t RHCP RAS tT t CSH t RCD UCAS LCAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RP
Address
Row
Column t RCS t RCS t RCH
Column t RCS t RCH
Column t RRH t RCH
WE t CDD t DZC High-Z t ODD t CAC t AA t RAC t OFF1 Dout High-Z t DZO t OAC t DZO t OFF2 OE Dout t AA t ACP t OFF1 t DZC t CDD High-Z t CAC High-Z t CAC t AA t ACP t DZO Dout t ODD t OFF2 t OAC t OFF2 t OFF1 t ODD t DZC
t CDD
Din
Dout
t OAC
21
HM514260C, HM51S4260C Series
Fast Page Mode Early Write Cycle
t RASC t RP
RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
UCAS LCAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH
Address
Row
Column t WCS t WCH
Column t WCS t WCH t WCS
Column
t WCH
WE t DS t DS t DH t DH t DS t DH
Din
Din
Din
Din
Dout
High-Z
* OE : H or L
22
HM514260C, HM51S4260C Series
Fast Page Mode Delayed Write Cycle
t RASC
t RP
RAS t CSH tT t RCD UCAS LCAS t ASR t RAH t ASC t CAH t ASC t CAH t CWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t ASC t CAH
Address
Row
Column
Column
Column
t CWL t RCS t WP t WP
t CWL t WP t RWL
WE t DH t DS t RCS t DS t DH t RCS t DS t DH
Din
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
23
HM514260C, HM51S4260C Series
Fast Page Mode Read-Modify-Write Cycle
t RP
t RASC RAS t RCD tT t CP t PCM t CP
t CRP
UCAS LCAS t ASR
t RAD t RAH t CAH t ASC t ASC
t ACP t CAH t CAH t ASC
Address
Row
Column t AWD t CWD t RWD t CWL t WP
Column t AWD t RCS t CWD t CPW t WP t CWL
Column t CPW t AWD t RCS t CWD t CWL t RWL t WP
t RCS
WE t DS t DZC t CAC t DH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t OEH t OAC Dout t OFF2 t OEH
t DS t DH
Din
High-Z t AA t RAC t OAC
Din t DZO t OEH
High-Z t AA t OAC Dout t OFF2
Din
Din
Dout t DZO
Dout t OFF2
t DZO
OE t ODD t ODD t ODD
24
HM514260C, HM51S4260C Series
Self Refresh Cycle
t RP
t RASS
t RPS
RAS tT t RPC t CPN UCAS LCAS t CRP t CSR t CHS
Address t OFF1 Dout High-Z 25
* WE, OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 2. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.
HM514260C, HM51S4260C Series
Package Dimensions
HM51(S)4260CJ/CLJ Series (CP-40DA)
Unit: mm
25.80 26.16 Max 40 21 10.16 0.13 0.74
1.30 Max 3.50 0.26
1
20
11.18 0.13
0.43 0.10
1.27 0.10
0.80
9.40 0.25
26
2.85 0.12
+0.25 -0.17
HM514260C, HM51S4260C Series
HM51(S)4260CTT/CLTT Series (TTP44/40DB)
Unit: mm
44
18.41 18.81 Max 35 32
23
1
10 13 0.80 0.13 M 1.005 Max
22
0.27 0.07
10.16
11.76 0.20 0 - 5 0.13 0.05
+0.075 -0.025
1.20 Max
0.10
0.145
0.50 0.10
27
0.68
0.80

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